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We will describe the main features of this technology, including an overview of offered photonic and electronic devices. Among these circuits are a 40Gbps monolithically integrated linear receiver [4] and a monolithically integrated segmented driver and Mach-Zehnder modulator with 13 dB extinction ratio at 28 Gbps [5]. We will also present our work to integrate a new Ge photodiode with 70GHz bandwidth and to improve the bipolar transistor performance to enable the fabrication of integrated receivers and transmitters with strongly increased optical line rates [6, 7].

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Abstract Silicon-based electronic-photonic integrated circuit ePIC technology enables a high degree of integration of optoelectronic sub-systems for optical communications. This Article Meet. Services Email this article to a colleague Alert me when this article is cited Alert me if a correction is posted Article Usage Statistics Similar articles in this journal Similar articles in Web of Science Download to citation manager Permission requests. Google Scholar Articles by Knoll, D. Articles by Zimmermann, L.

Search for related content. PubMed Articles by Knoll, D. Related Content Load related web page information Related Article. With this new HBT generation it becomes conceivable to extend fundamental operating frequencies of integrated silicon circuits up to GHz which is out of reach with existing technologies. The available wide absolute band width at these frequencies will enable, e. High-precision radar and imaging systems can take advantage of the corresponding reduction of the carrier wave length. This paper addresses advances in device fabrication technology and device scaling that facilitated the remarkable improvement of RF performance.

The impact of device geometries, specific material characteristics, and process integration aspects on device performance is discussed in section 2 for three HBT generations. Section 4 addresses the impact of using the higher order precursor gas disilane instead of silane for the epitaxial growth of the base layer stack. Consequences on scalability and device performance are discussed. Figure 1. Transit frequency f T versus collector current density for three HBT generations.

Figure 2. The achieved performance enhancement was made possible by scaling vertical and lateral transistor dimensions and a series of process innovations which helped to reduce non-scaling contributions to device parasitics such as base and emitter resistances. A major feature size for HBT scaling is the emitter width. These values are still far from the scaling limit indicating room for performance improvement by further device scaling. Figures 1 and 2 indicate that the roll-off of f T and f MAX is shifted to higher current densities for the advanced technology generations.

This is due to an enhanced dopant concentration in the collector region which suppresses the base-push-out effect. As a consequence, peak values of f T and f MAX shift to higher current densities for the advanced technology generations. However, it can be seen also that the advanced technologies provide significantly higher values of f T and f MAX than previous generations for a given collector current density. The higher f T and f MAX values correspond to higher current gain and power gain for transistor operation at a given application frequency thus enhancing the design margin for circuit applications at this frequency.

The reduction of breakdown voltages due to the more aggressive doping profiles of the advanced transistor generations was moderate. The emitter-collector breakdown voltages BV ECo are 1. The high-speed performance of a technology for switching operation can be efficiently benchmarked by ring oscillator gate delays. Gate delays of current-mode-logic CML ring oscillators are plotted in figure 3 as a function of collector current density for the three technology generations.

The oscillators consist of 31 stages and a frequency divider. Figure 3 indicates that the improved f T and f MAX values of the advanced HBT generations are associated with significantly reduced gate delay times. The minimum gate delay of 1. Shorter gate delays have not been reported for any other integrated circuit technology.

130 nm SiGe BiCMOS Processes Optimize Cost and Performance

Figure 3. In this section, we review the process developments that facilitated the improved RF performance of the DOT7 device with respect to the SG13G2 reference process. The introduced process modifications addressed the reduction of device parasitics by reducing lateral device dimensions as well as by improving the control of the doping profile and the conductivity of critical device regions.

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Further details of this process optimization and results for individual device parameters are given in [ 1 , 7 ]. A schematic cross section of the HBT is given in figure 4.

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Basic features common to all three HBT generations are: i elevated extrinsic base regions self-aligned to the emitter window resulting in low base resistance, ii the formation of the HBT in a single active area without shallow trench isolation STI between emitter and collector contacting regions resulting in low collector resistance and small collector-substrate junction areas, and iii the absence of epitaxially-buried subcollectors and deep trenches in order to limit process complexity. Low-resistive collector wells isolated by standard STI are formed by ion implantation and rapid thermal annealing at the beginning of the HBT process module.

Critical lateral dimensions such as the width of the emitter window w E , the width of the collector window w C , the width of the emitter poly-silicon w EP and the width of the base-emitter spacer d Sp are indicated. Details of the fabrication process and depth profiles of the doping and germanium concentrations of the advanced transistor generation can be found in chapters 1.

Skal 45 - CMOS or BiCMOS Process Technology

The fabrication process includes the following four epitaxial steps. Subsequently, masked ion implantation is used to form the selectively-implanted collector SIC in the inner transistor region. Figure 4. Schematic cross section of the HBT. Key device dimensions are indicated.

The realization of high f MAX values requires high cutoff frequencies f T together with low base resistance R B and low base-collector capacitance C BC as indicated by the relation. High f T values are facilitated by steep vertical doping profiles with short transit times through the base and the base-emitter and base-collector junctions combined with short charging times of the base-emitter and base-collector capacitances.

An enhanced arsenic concentration and a reduced thickness of the emitter helped to reduce the emitter resistance. Consequently, low base-emitter and base-collector charging times could be maintained despite of the enhanced capacitances due to reduced junction widths. The broadening of the doping profiles was minimized by reducing the spike temperature for the final rapid thermal process.

All three technology generations take advantage of the suppressed diffusion of boron due to carbon doping. A further process modification that helped to reduce the excess resistances of base, emitter, and collector was the introduction of a millisecond flash-annealing step combined with a low-temperature back-end-of-line process with nickel silicide. Heating the wafer surface to temperatures close to the melting point at a millisecond time scale results in strongly enhanced dopant activation in heavily doped device regions without noticeable diffusion.

The thermal budget after ms-annealing has to be minimized in order to avoid dopant deactivation. This is supported by the replacement of the CoSi 2 process by a NiSi process with lower thermal budget. An additional reduction of R B was achieved by optimizing the process for the selective epitaxial growth and by increasing the dopant concentration of the elevated external base regions.

Critical lateral dimensions such as w E , w C , and w EP were reduced for the DOT7 devices see figure 5 by reducing the corresponding lithographic dimensions. However, the possibilities for scaling the emitter window by lithographic measures are limited by the resolution of the used nm DUV scanner. Therefore, w E could be scaled only moderately from to nm. The width of base-emitter spacers was reduced for the DOT7 device by modifying the corresponding etching and deposition processes.

In addition, the width of the silicide blocking spacers at the outside of the emitter poly was reduced for the DOT7 device. Moreover, the process for the SIC that is formed before base epitaxy in the collector region below the emitter window was changed from a resist mask in SG13G2 to a hard mask process in DOT7 allowing for an improved control of the width and the doping concentration of the SIC region. Figure 5. A crucial step of the HBT fabrication is the epitaxy of the base layer stack.

At the beginning of this epitaxial process, the wafers are covered with an about 80 nm thick oxide layer except for small collector windows of width w C. These collector windows were filled with Si up to the level of the oxide surface by a preceding selective epitaxial process. We have investigated two processes options for the epitaxy of the base layer stack which use silane and disilane as Si precursor gases, respectively.

The replacement of silane by the higher order precursor disalane results in significantly higher growth rates.

Process technology

As a consequence, lower deposition temperatures are applicable for the disilane process. Next, the two processes are analyzed with respect to their potential for lowest base resistance and device scaling. Figure 6 shows scanning electron microscopy SEM images of HBTs after deposition of the base layer stack using silane-based and disilane-based epitaxy. Silane epitaxy figure 6 a results in crystalline growth on Si areas and poly-crystalline growth on oxide areas.

The grain structure of the poly-crystalline layer causes a rough transition line between the poly-crystalline and single-crystalline areas as indicated in figure 6 a.